1. Field of the Invention
The present invention pertains to a method for adjusting a semiconductor device threshold voltage during device fabrication, and more particularly to adjusting the threshold voltage of a vertical double diffused MOSFET ("VDMOS") transistor during fabrication by high energy ion implantation through the gate thereof.
2. Description of Related Art
The threshold voltage V.sub.t for MOSFET transistors is defined as the voltage V.sub.gs applied between gate and source, below which the MOS transistor drain-to-source current I.sub.ds becomes zero. The threshold voltage for n-channel and p-channel devices are denoted V.sub.tn and V.sub.tp, respectively. The threshold voltage is a function of a number of parameters, including the gate material, the gate insulation material, the gate insulator thickness, the channel doping, the impurities at the silicon-insulator interface, and the voltage V.sub.sb between the source and substrate.
In particular, in double diffused transistors, the net channel concentration is formed by the sequential diffusion of source and body implants self-aligned to a polysilicon gate. Without the use of self-alignment to the gate, an unacceptable variation in V.sub.t will result. Reduction in the threshold voltage of a DMOS transistor may be achieved by lowering the body implant dose, which reduces the effective channel concentration, or by driving the source deeper to compensate a greater portion of the body doping profile. Another approach is to make the body diffusion shallow relative to the source diffusion, so that the body diffusion concentration is compensated by the source diffusion concentration.
Adjusting the threshold by these means is limited by a number of potentially adverse or catastrophic complications in the device. As the net body concentration is reduced, the likelihood of punch through breakdown is exacerbated. This limitation can be particularly troublesome in lower voltage DMOS (e.g. 20 volt to 60 volt breakdowns) where the depletion spreading in the body from the reverse-biased drain to the body junction is significant. Beyond punch through problems, lighter net body doping results in an increase in the parasitic bipolar gain of the bipolar transistor formed by the source acting as the emitter, the body acting as the base, and the drain acting as the collector. In an n-channel vertical DMOS, a parasitic NPN transistor is present, whereas in a p-channel DMOS, a parasitic PNP transistor is present. The effect of this parasitic transistor is to cause potentially destructive snap-back breakdown, since the BV.sub.ceo breakdown of the bipolar transistor is lower than the BV.sub.DSS of the MOSFET transistor (equivalent to the BV.sub.CES in the bipolar). Decreasing the net charge in this parasitic base both increases the parasitic bipolar gain, thereby lowering the snap-back voltage; and increases the base resistance, thereby making the bipolar transistor easier to turn on. Moreover, as junctions are scaled to more shallow dimensions, the sensitivity of the net charge to process variations is increased. The net effect of low body doping, then, is an increased sensitivity to snap-back, a decrease in the safe operating area of the device, a possible reduction in the break down of the device, and a reduction in the ruggedness capability (i.e. the ability to survive an unclamped inductive switching ("UIS") transient.
Generally, therefor, a vertical DMOS is made robust by using a higher body concentration, not a lower value. Unfortunately, a higher body concentration corresponds to higher thresholds. This problem is particularly true for p-channel DMOS transistors, which have a higher threshold for a given channel concentration than a comparable n-channel DMOS. The higher threshold occurs as a result of the positive charge in the oxide and the gate to silicon work function, particularly when an N-type polysilicon gate is used. The higher threshold is a particular disadvantage in low gate drive applications such as applications in which the MOS gate drive supply voltage is 5 volts or below. Moreover, a high threshold for a p-channel DMOS transistor further degrades performance relative to the n-channel DMOS transistor, particularly since p-channel devices are less efficient due to the mobility effect alone.
Known techniques for threshold adjust are not entirely satisfactory for use in VDMOS processes, and particularly in p-channel DMOS. Channel doping is a well known technique for threshold adjustment. Channel doping involves varying the doping concentration at the silicon-insulator interface. In CMOS processes, channel doping typically is done prior to deposition of the gate polysilicon. Generally, the technique is not applicable to processes in which two and possibly more successive diffusions are used, such as processes that include steps for fabricating DMOS devices in which a body region must be diffused deeper than a source. Specifically, in a vertical DMOS transistor, the channel region requiring threshold adjusting is double-diffused. Impurity distribution in diffusion processes is dependent on the product of the diffusion coefficient D(T) and the time, or .sqroot.Dt (hereinafter "root Dt"). In double diffused MOSFET devices, the root Dt is large, ranging from 0.3 or 0.4 microns all the way down to 1.0 or 1.5 microns. When exposed to such large root Dt values, the threshold dopant diffuses too deeply into the double-diffused channel, forming a leakage path between the diffused source and the epitaxial drain of the vertical DMOS MOSFET which is not pinched off at V.sub.gs =0.
The necessity for using only low temperature processing following the channel doping step has been a significant motivating factor in classical VLSI and integrated circuit process design. Unfortunately, conventional techniques of threshold adjusting prior to gate formation are incompatible with the self-aligned double diffused MOSFET.
Another conventional technique for reducing V.sub.tp of a PMOS device, one which is useful even in processes having long diffusion times after the polysilicon deposition step, is to use boron-doped p-type polysilicon gates in association with the PMOS devices, instead of phosphorus-doped n-type polysilicon gates. The p-type polysilicon has a different work function, so that the threshold of the PMOS devices is shifted by about a volt. Unfortunately, this technique is not entirely satisfactory for use in processes specifying a thin gate oxide, as the boron from the p-type polysilicon penetrates easily through the thin gate oxide in any subsequent diffusion steps and can counterdope the channel. Leakage and other problems result. Moreover, this problem is exacerbated by the presence of hydrogen. While the risk is reduced by the use of a thicker gate oxide, say on the order of 1000 .ANG., the requirement for a thicker gate oxide compromises process flexibility and device performance.
A need, therefor, exists for a technique for adjusting the V.sub.t of VDMOS FET devices and in particular p-channel VDMOS devices while preserving the ability to use long diffusion and high temperature steps subsequent to polysilicon gate deposition.